An energy optimal power supply for digital circuits

Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2006.Includes bibliographical references (p. 96-98).The energy efficiency of digital circuits continues to be a major factor in determining the size and weight of battery-operated electronics. Integration of more functionality in a single system has made battery longevity a major problem. Operating circuits at their minimum energy operating voltage (MEP) has been proposed as a solution for energy critical applications where performance is not a key constraint. This thesis explores the sensitivity of the MEP to operating conditions and motivates the need for continuous minimum energy tracking based on the energy savings possible. A circuit that can dynamically track the MEP of a digital circuit with varying load conditions and temperature is presented. A low power, voltage scalable DC-DC converter is also embedded within the chip. The proposed minimum energy tracking algorithm uses a novel approach to sense the energy consumed per operation. The energy sensing circuitry does not use high-resolution Analog-to-Digital converters or high gain amplifiers. The energy estimate is used in a slope tracking algorithm to track the minimum energy operating voltage. The minimum energy tracking loop along with a low-voltage DC-DC converter and test circuitry were fabricated in a 65nm CMOS process.(cont.) The circuits are powered from an external 1.2V supply. The digital test circuitry was capable of operation at voltages as low as 0.25V. The tracking of the minimum energy operating voltage with change in workload and temperature was observed. The DC-DC converter was able to deliver load voltages between 0.25V and 0.7V with an efficiency > 78% at load power levels of the order of 1 0.1W and above.by Yogesh Kumar Ramadass.S.M

Energy processing circuits for low-power applications

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2009.Cataloged from PDF version of thesis.Includes bibliographical references (p. 199-205).Portable electronics have fueled the rich emergence of new applications including multi-media handsets, ubiquitous smart sensors and actuators, and wearable or implantable biomedical devices. New ultra-low power circuit techniques are constantly being proposed to further improve the energy efficiency of electronic circuits. A critical part of these energy conscious systems are the energy processing and power delivery circuits that interface with the energy sources and provide conditioned voltage and current levels to the load circuits. These energy processing circuits must maintain high efficiency and reduce component count for the final solution to be attractive from an energy, size and cost perspective. The first part of this work focuses on the development of on-chip voltage scalable switched capacitor DC-DC converters in digital CMOS processes. The converters are designed to deliver regulated scalable load voltages from 0.3V up to the battery voltage of 1.2V for ultra-dynamic voltage scaled systems. The efficiency limiting mechanisms of these on-chip DC-DC converters are analyzed and digital circuit techniques are proposed to tackle these losses. Measurement results from 3 test-chips implemented in 0.18pm and 65nm CMOS processes will be provided. The converters are able to maintain >75% efficiency over a wide range of load voltage and power levels while delivering load currents up to 8mA. An embedded switched capacitor DC-DC converter that acts as the power delivery unit in a 65nm subthreshold microcontroller system will be described. The remainder of the thesis deals with energy management circuits for battery-less systems. Harvesting ambient vibrational, light or thermal energy holds much promise in realizing the goal of a self-powered system. The second part of the thesis identifies problems with commonly used interface circuits for piezoelectric vibration energy harvesters and proposes a rectifier design that gives more than 4X improvement in output power extracted from the piezoelectric energy harvester. The rectifier designs are demonstrated with the help of a test-chip built in a 0.35pm CMOS process. The inductor used within the rectifier is shared efficiently with a multitude of DC-DC converters in the energy harvesting chip leading to a compact, cost-efficient solution. The DC-DC converters designed as part of a complete power management solution achieve efficiencies of greater than 85% even in the micro-watt power levels output by the harvester. The final part of the thesis deals with thermal energy harvesters to extract electrical power from body heat. Thermal harvesters in body-worn applications output ultra-low voltages of the order of 10's of milli-volts. This presents extreme challenges to CMOS circuits that are powered by the harvester. The final part of the thesis presents a new startup technique that allows CMOS circuits to interface directly with and extract power out of thermoelectric generators without the need for an external battery, clock or reference generators. The mechanically assisted startup circuit is demonstrated with the help of a test-chip built in a 0.35pm CMOS process and can work from as low as 35mV. This enables load circuits like processors and radios to operate directly of the thermoelectric generator without the aid of a battery. A complete power management solution is provided that can extract electrical power efficiently from the harvester independent of the input voltage conditions. With the help of closed-loop control techniques, the energy processing circuit is able to maintain efficiency over a wide range of load voltage and process variations.by Yogesh Kumar Ramadass.Ph.D

An efficient piezoelectric energy-harvesting interface circuit using a Bias-Flip rectifier and shared inductor

Energy harvesting is an emerging technology with applications to handheld, portable and implantable electronics. Harvesting ambient vibration energy through piezoelectric (PE) means is a popular energy harvesting technique that can potentially supply 10 to 100's of muW of available power. One of the limitations of existing PE harvesters is in their interface circuitry. Commonly used full-bridge rectifiers and voltage doublers severely limit the electrical power extractable from a PE harvesting element. Further, the power consumed in the control circuits of these harvesters reduces the amount of usable electrical power. In this paper, a bias-flip rectifier that can improve upon the power extraction capability of existing full-bridge rectifiers by up to 4.2times is presented. An efficient control circuit with embedded DC-DC converters that can share their filter inductor with the bias-flip rectifier thereby reducing the volume and component count of the overall solution is demonstrated. The circuit diagram and figures are also given

A batteryless thermoelectric energy-harvesting interface circuit with 35mV startup voltage

A batteryless thermoelectric energy-harvesting interface circuit to extract electrical energy from human body heat is implemented in a 0.35 μm [mu m] CMOS process. A mechanically assisted startup circuit enables operation of the system from input voltages as low as 35 mV. A control circuit that performs maximal transfer of the extracted energy to a storage capacitor and regulates the output voltage at 1.8 V is presented.Massachusetts Institute of Technology. Energy Initiativ

A Fully-Integrated Switched-Capacitor Step-Down DC-DC Converter With Digital Capacitance Modulation in 45 nm CMOS

Implementing efficient and cost-effective power regulation schemes for battery-powered mixed-signal SoCs is a key focus in integrated circuit design. This paper presents a fully-integrated switched-capacitor DC-DC converter in 45 nm digital CMOS technology. The proposed implementation uses digital capacitance modulation instead of traditional PFM and PWM control methods to maintain regulation against load current changes. This technique preserves constant frequency switching while also scaling switching and bottom-plate losses with changes in load current. Therefore, high efficiency can be achieved across different load current levels while maintaining a predictable switching noise behavior. The converter occupies only 0.16 mm2, and operates from 1.8 V input. It delivers a programmable sub-1 V power supply with efficiency as high as 69% and load current between 100 μA and 8 mA. Measurement results confirm the theoretical basis of the proposed design

A 65 nm Sub- V_{t} Microcontroller With Integrated SRAM and Switched Capacitor DC-DC Converter

Aggressive supply voltage scaling to below the device threshold voltage provides significant energy and leakage power reduction in logic and SRAM circuits. Consequently, it is a compelling strategy for energy-constrained systems with relaxed performance requirements. However, effects of process variation become more prominent at low voltages, particularly in deeply scaled technologies. This paper presents a 65 nm system-on-a-chip which demonstrates techniques to mitigate variation, enabling sub-threshold operation down to 300 mV. A 16-bit microcontroller core is designed with a custom sub-threshold cell library and timing methodology to address output voltage failures and propagation delays in logic gates. A 128 kb SRAM employs an 8 T bit-cell to ensure read stability, and peripheral assist circuitry to allow sub-Vt reading and writing. The logic and SRAM function in the range of 300 mV to 600 mV, consume 27.2 pJ/cycle at the optimal V [subscript DD] of 500 mV, and 1 muW standby power at 300 mV. To supply variable voltages at these low power levels, a switched capacitor DC-DC converter is integrated on-chip and achieves above 75% efficiency while delivering between 10 muW to 250 muW of load power.Defense Advanced Research Projects Agenc

A 0.16mm2 completely on-chip switched-capacitor DC-DC converter using digital capacitance modulation for LDO replacement in 45nm CMOS

A completely on-chip switched-capacitor DC-DC converter that occupies 0.16 mm2 [mm superscript 2] is implemented in a 45 nm CMOS process. The converter delivers 8 mA output current while maintaining load voltages from 0.8 to 1 V from a 1.8 V input supply. A digital capacitive modulation scheme is employed to maintain the converter efficiency between 50 to 70% over a wide range of load current levels

Technologies for Ultradynamic Voltage Scaling

Energy efficiency of electronic circuits is a critical concern in a wide range of applications from mobile multi-media to biomedical monitoring. An added challenge is that many of these applications have dynamic workloads. To reduce the energy consumption under these variable computation requirements, the underlying circuits must function efficiently over a wide range of supply voltages. This paper presents voltage-scalable circuits such as logic cells, SRAMs, ADCs, and dc-dc converters. Using these circuits as building blocks, two different applications are highlighted. First, we describe an H.264/AVC video decoder that efficiently scales between QCIF and 1080p resolutions, using a supply voltage varying from 0.5 V to 0.85 V. Second, we describe a 0.3 V 16-bit micro-controller with on-chip SRAM, where the supply voltage is generated efficiently by an integrated dc-dc converter.Natural Sciences and Engineering Research Council of Canada (NSERC)Texas Instruments Incorporated (Texas Instruments Graduate Women’s Fellowship for Leadership in Microelectronics)Intel Corporation (Intel Ph.D. Fellowship Program)Texas Instruments IncorporatedNokia CorporationSemiconductor Research Corporation . Focus Center for Circuit and System Solutions (C2S2)United States. Defense Advanced Research Projects Agenc